Panel & Session Details

Discussing Todays Hottest Logic NVM Topics

Panel Discussion
Room: Santa Clara Ballroom
Configuring Your NVM
The starting point for embedded non-volatile memory can be confusing for a designer. Lots of questions seem to crop up. For example, what exactly should you be embedding into that memory die, and what are the tradeoffs that come with those decisions. Should you be thinking about embedding the memory into the logic, or vice versa, and why? Should your memory include a one-time programmable (OTP) section or should it be "multiple-time" programmable? What are the strengths and weaknesses of adding just a few bytes of memory, and what are the "must-have" features? These are the questions that will be answered by this esteemed panel, as well as any others that you are welcome to ask.

Moderated by: Alan Niebel, Founder and CEO of Web-Feet Research, a semiconductor market research company located in Monterey, CA.
Panel:
Todd Humes, Vice President of Engineering IP Products, Impinj
Charles Ng, Vice-President of Worldwide Sales & Marketing, Kilopass Technology
Joel Rosenberg, Sr. Director of Digital Consumer Marketing, Virage Logic
Rick Shen, Vice President of Operation and Technology Development, eMemory
Xerxes Wania, CEO and President, Sidense

Conference Tracks

The Technology Track looks at the underlying physics and process technologies that are supporting Logic NVM today, tomorrow, and well into the future.

Time Session

1:00 - 1:40pm Few-Times Programmable (FTP) Logic NVM
Room: Lafayette
Speaker: Todd Humes, Vice President of Engineering IP Products, Impinj

The architecture for a few-time programmable (FTP) NVM bridges the gap between one-time programmable (OTP) memories and high cycle count, high reliability multiple time programmable (MTP) NVM. Use models requiring lower write cycle counts (<100 cycles) will benefit in several ways: 1) higher memory density, 2) 100% factory testable, and 3) reprogrammability. The fundamental technology requirements for meeting these requirements such as intrinsic retention, error correction and cycling trade-offs will be discussed against traditional high cycle count NVM.

1:50 - 2:30pm More Information Coming Soon
Room: Lafayette
Speaker: TBD

The Applications Track includes real examples of how Logic NVM is being used in Power Management, Digital Rights Management, and Silicon Clocks. Expect more of the same this year with users of Logic NVM IP providing examples of the benefits and opportunities enabled by integrating Logic NVM in their design.

Time	Session
1:00 - 1:40pm	Cryptographic Authentication Through RSA Digital Signature Algorithms Room: San Thomas Speaker: Al Hawtin, Elliptic Seminconductor Cryptographic authentication through RSA digital signature algorithms are used both for secure boot and for anti-cloning technologies in SoC designs. Secure boot ensures that the system loads only the code which is factory authorized and prevents hackers from modifying the system code in Flash and taking control of the product for malicious reasons. Anti-cloning techniques use embedded secrets in the device to ensure that only authorized systems will function correctly. The presentation explains the cryptographic design used to achieve these features as well as the NVM solutions best suited to the task of storing the embedded secrets required for these two applications.
1:50 - 2:30pm	Logic NVM for Precision Analog and Timing Circuits in CMOS Room: San Thomas Speaker: Michael S. McCorquodale, Ph.D., Chief Technical Officer, Mobius Microsystems The use of high-resolution analog current, voltage and switched-capacitor trimming has proven critical to the development of Mobius’ self-referenced CMOS oscillator technology for quartz crystal replacement. Mobius’ components are the highest-accuracy all-CMOS frequency references on the market. The use of logic NVM in Mobius’ timing products is discussed within the general context of storing trimming and configuration coefficients for precision analog components.

The Integration Track targets the designer who is in the trenches making sure that the Logic NVM IP is integrated properly into the overall design. We will review the common pitfalls associated with Logic NVM integration, give advice on how to plan the integration process to ensure a smooth and successful product development, and explore some of the lessons that others have learned while integrating Logic NVM into their design.

Time

Session

1:00 - 1:40pm

Design Selection Alternatives for Integrated Memory
Room: Lawrence
Speaker: Gregory A. Quirk, Product Manager, TechOnline

Logic NVM is one of many different alternatives for designers to provide some memory capabilities without incorporating a separate component, such as an EEPROM or DRAM. But why would you choose logic NVM over another solution? How does it compare to popular choices like embedded flash and fuse/antifuse technologies? The presentation will provide an overview of these three solutions and provide comparison and contrasts between them using technical in depth detailed analysis from Semiconductor Insights. As well, an overview of the intellectual property (IP) for logic NVM will be discussed and some of the more open spaces for further development identified.

The Quality and Reliability Track will dig into the qualification and characterization methodologies that are unique to embedded NVM in general and Logic NVM in particular. This track will cover topics ranging from industry standards for qualification testing to reliability modeling efforts and techniques.

Time	Session
1:50 - 2:30pm	Logic NVM Technologies: IP Qualification Requirements and Methods Room: Lawrence Speaker: Pearl Cheng, Vice President of Engineering and Operations, Kilopass There are three primary categories of non-volatile memory technology developed on standard logic CMOS process technologies: fuse, anti-fuse, and floating gate. The intrinsic nature of all of three of these technologies is to either effect a physical, and, thereby, electrical change in a semiconductor material or to store a charge within a floating gate in order to store information. The storage mechanisms involve effects on CMOS device materials that are not necessarily intended by the wafer manufacturer. Although there is a substantial investment required, it is critical that Logic NVM IP vendors qualify their technologies in order to provide necessary quality and reliability assurances, as well as protections to the end customer. This presentation discusses the qualification requirements and methods needed for the qualification of Logic NVM IP technologies as well as the underlying benefit to the end customer provided with this qualification information.
3:00 - 3:40pm	Logic NVM with Sub 1 PPM Reliability Room: Lafayette Speaker: Bin Wang, Ph.D., Technology Transfer Manager, Impinj Product reliability can be enhanced by various design-for-reliability techniques such as redundancy, ECC, layout, etc. This talk focuses on first theoretical statistical analysis on product failure rate versus single floating gate (FG) failure rate for FG logic NVM (LNVM). It shows step-by-step how reliability is enhanced. Second, it demonstrates that sub 1 PPM reliability can be achieved for LNVM with 70 tunneling oxide based on experimental data. Lastly, trade-offs between reliability levels and architectures are discussed.
3:00 - 3:40pm	Reliability Characterization Challenges and Methodologies for OTP Memory Arrays Room: San Thomas Speaker: Wlodek Kurjanowicz, CTO, Sidense Embedded one-time programmable (OTP) memory has been employed for several years as an inexpensive and relatively easy-to-implement storage mechanism. Traditional technologies such as ROM and eFuse have been in widespread use, but limitations with regard to field-programmability, long-term reliability and storage security have prompted several vendors to investigate other OTP mechanisms for implementing embedded data and code storage. This has led to the introduction by several vendors of antifuse-based embedded OTP memory IP, some using oxide breakdown as a way to program memory bits. This tutorial reviews OTP qualification challenges and describes an effective reliability test methodology used for memory arrays based on a unique split-channel OTP bit cell. The tutorial will also include associated silicon test results.
3:00 - 3:40pm	Reliable Multi-time Programmable NVM on Advanced Process Nodes Room: Lawrence Speaker: Dave Sowards, VP NVM Products Embedded one-time programmable (OTP) memory has been employed for several years as an inexpensive and relatively easy-to-implement storage mechanism. Traditional technologies such as ROM and eFuse have been in widespread use, but limitations with regard to field-programmability, long-term reliability and storage security have prompted several vendors to investigate other OTP mechanisms for implementing embedded data and code storage. This has led to the introduction by several vendors of antifuse-based embedded OTP memory IP, some using oxide breakdown as a way to program memory bits. This tutorial reviews OTP qualification challenges and describes an effective reliability test methodology used for memory arrays based on a unique split-channel OTP bit cell. The tutorial will also include associated silicon test results.

The Testability Track will look into how to get your finished design into full production by minimizing overall test cost, while still meeting all your required quality and reliability metrics. We will look at common trade-offs of test time versus coverage and how to integrate the Logic NVM test requirements into your overall SoC test plan.

Time	Session
3:00 - 3:40pm	Embedded Non-Volatile Memory with Efficient Testability Room: Lawrence Speaker: TBD An Embedded Non-Volatile multi-programmable solution has been developed with several features that facilitate efficient testability. The Page programming feature provides a very efficient method of storing many bits in parallel thereby minimizing test time and cost. The Margin mode provides a simple expedient method of monitoring the program margin for all bits in the array. The Vt distribution test allows for the measurement of programming threshold voltages for every individual bit thereby facilitating efficient product qualification. The product has been successfully developed in 130 nm and 90 nm technologies and results will be shown.
3:50 - 4:30pm	Production Test Methodology for Manufacturable NVM Room: Lawrence Speaker: Martin Niset, Product and Test Engineering Manager, Impinj The ideal production test flow guarantees that the device under test meets all the datasheet specifications while keeping test time at a minimum. Achieving such a feat with an NVM array presents many challenges including: (1) validating the electrical performance across temperature, (2) guaranteeing key end of life reliability metrics such as data retention and (3) managing test time regardless of the array size. This paper addresses test strategy and unique Design For Test features required to meet those challenges.

View the complete agenda.

2007 Panel & Session Details

Panel Discussion & Debate
The Logic NVM 2007 brings together authorities on logic nonvolatile memory (NVM) technology to discuss and debate today's hottest topics – applications, markets, trends and predictions, best practices, challenges, and much more. The panel will be moderated by iSuppli Corporation Semiconductor Analyst Jordan Selburn and will feature:

PDF Files

Larry Morrell, Vice President IP Products, Impinj, Inc.
PDF-VIEW PRESENTATION

Charles Ching-Hsiang Hsu, President, eMemory Technology Inc.
PDF-VIEW PRESENTATION

Charles Ng, Vice President of Worldwide Sales and Marketing, Kilopass
PDF-VIEW PRESENTATION

Walter Ng, Senior Director, Platform Alliances, Chartered Semiconductor Manufacturing
PDF-VIEW PRESENTATION

David Sowards, Vice President of Non-Volatile Memory Products, Virage Logic

Xerxes F. Wania, President and Chief Executive Officer, Sidense Corporation
PDF-VIEW PRESENTATION

Audio Files

Part 1 – Logic NVM Event keynote by Jack Harding and panel discussion (1 hour, 20 minutes)
Part 2 – Panel discussion continued… (14 minutes)
Part 3 – Panel discussion continued… (1 hour, 5 minutes)
Part 4 – Panel discussion continued… (8 minutes)

Keynote Presentation
Jack Harding, Chairman, President and CEO, eSilicon Corporation
Smaller, Faster, Cheaper, Better: The Relentless Pressure on Consumer Electronics
PDF-VIEW PRESENTATION

Closing Remarks

Audio File

Logic NVM Event wrap up & thank you - Larry Morrel (3 minutes)

Breakout Sessions
Informative breakout sessions take place following the agenda of morning activities, consisting of the keynote presentation by eSilicon's Jack Harding, panel discussion, and lunch.

The three breakout session tracks are:

Quality & Reliability
NVM Core Technology & Physics
Market & Applications

PDF Files

Quality and Reliability:

FSA Hard IP Quality Risk Assessment Tool
By Lisa Tafoya, VP Global Research, FSA
PDF-VIEW PRESENTATION

Abstract:
FSA has developed an IPecosystem Tool Suite, designed to provide engineering and business guidance for hard IP risk assessments. The goal is to provide companies purchasing IP with a more efficient means of integrating and utilizing IP at various intervals: pre-purchase, licensing, design and manufacturing. FSA's Hard IP Quality Risk Assessment Tool, the first tool introduced in the Suite, consists of a set of questions for categories of IP interaction that communicate the quality aspects of an IP core, and it develops a risk profile for integrators to evaluate the quality of the IP. This can be applied to its original focus of third-party IP, or can be used for evaluating internally developed IP for reuse in other designs. In addition, it allows both integrators and vendors to compare all of their IP to an industry best practices baseline for quality.

Qualification and Reliability of Logic NVM
By David Sowards, VP Nonvolatile Memory Products, Virage Logic

Abstract:
Virage Logic will present an overview of qualification requirements, including why qualification is done in the first place. Topics such as temperature acceleration and its use in qualification will be discussed. Topics relating to reliability, such as cycling and data retention, will also be covered.

Kilopass XPM Reliability Assurance Process and Methods
By Harry Luan, Ph.D., Director of Technology, Kilopass
PDF-VIEW PRESENTATION

Abstract:
Since embedded non-volatile memory (NVM) technologies rely on a combination of analog and digital circuits, understanding the effects of the embedded NVM technology’s basic read and write functions over time on the underlying process technology’s reliability is critical. This presentation will discuss the reliability of an antifuse one-time programmable NVM technology designed in standard logic CMOS with no additional mask or process steps. Reliability assurance of an antifuse OTP technology based on standard logic CMOS design rules through proper qualification processes and methodologies will also be addressed.

Automotive Level Reliability for Logic NVM
By Todd Humes, VP Engineering, Impinj, Inc.
PDF-VIEW PRESENTATION

Abstract:
For automotive applications, there are four major areas of concern: extreme environmental conditions, zero defect reliability, extended product lifetime, and performance. These requirements place unique challenges on embedded floating-gate NVM design and qualification. This presentation will discuss various design architecture techniques and qualification methodologies for meeting automotive requirements using logic NVM.

NVM Core Technology and Physics:

Logic NVM Challenges in Advanced Process Nodes
By Bin Wang, Ph.D., Technology Transfer Manager, Impinj, Inc.
PDF-VIEW PRESENTATION

Abstract:
Logic non-volatile memory (NVM) fits well for low-bit count application with very low manufacturing cost since it does not require adding extra masks or modifying process. This presentation will review its essentials and technology challenges at advanced technology nodes, with an emphasis on gate dielectric reliability and process compatibility. The focus will be on polysilicon floating gate memories. Knowledge-based qualification methodology on logic NVM will also be addressed.

Fundamentals of Gate Oxide Rupture NVM Technology
Wlodek Kurjanowicz, CTO, Sidense
PDF-VIEW PRESENTATION

Abstract:
Gate Oxide Rupture became an OTP technology of choice at 180nm, 130nm and 90nm nodes. At 65nm it becomes the only viable Logic NVM solution. This tutorial reviews the key milestones in gate oxide antifuse technology development, explains the fundamentals of the gate oxide breakdown mechanism and, for the first time, shows the characteristics of the Sidense high-density Split-channel 1T-Fuse™ memory cell suitable for the most advanced technology nodes.

SONOS Technology and its Implementation in a Logic Process
By Herman Lee, Business Development Manager, eMemory Technology
PDF-VIEW PRESENTATION

Abstract:
Since SoC applications have numerous needs of non-volatile memory (NVM), high density but cost effective embedded NVM technology becomes indispensable. SONOS technology is a promising technology which can perform full logic process compatibility and high portability. This presentation introduces the operation scheme, process technology and reliability performance of SONOS technology, whereas revealing its competitiveness in logic NVM field.

Embedded NVM Product Life Cycle Tradeoffs
By Mike Walach, Sales and Marketing Manager, Chingis Technology
PDF-VIEW PRESENTATION

Abstract:
While Logic NVM offers excellent embedded NVM performance using a standard logic process, improvements in endurance, power and die size may be achieved incrementally with the addition of mask layers. This presentation will examine some of the tradeoffs a designer should consider when choosing an NVM technology that supports a product's complete life cycle.

Markets and Applications:

Searching for Gold in New Designs
By Jordan Selburn, Principal Analyst, iSuppli Corporation
PDF-VIEW PRESENTATION

Abstract:

The number of ASSP and ASIC design wins has been on a steady decline for the past decade. Despite this trend – which iSuppli expects to continue – the market for these devices continues to grow at a rate even than other semiconductors. Key to winning new design sockets is identifying where the growth opportunities lie, and then putting together the appropriate infrastructure, particularly semiconductor IP, to address and capture those sockets. This presentation takes a look at the trends in ASSP and ASIC designs, providing attendees with insight into exciting areas of future opportunity.

NVM use in Security Applications
By Al Hawtin, Vice President Marketing and Business Development, Elliptic Semiconductor
PDF-VIEW PRESENTATION

Abstract:
The availability of non-volatile memory is pivotal for the implementation of security in SoCs targeted at markets such as consumer electronics, handsets and personal computers. ABI Research estimates that by 2013, 60 million consumer electronics devices will ship with hardware security cores. This session examines the drivers behind this rapid adoption in each market segment. The technical discussion offers details on how NVM is used for secure storage of keys and other secret values and guidelines on which NVM technology to choose to protect against reverse engineering attacks.

NVM use in Power Management
Steve Rivet, Product Line Director for Desktop and Server Power Management, Intersil
PDF-VIEW PRESENTATION

Abstract:
Modern microprocessors and other complex digital circuits require extremely accurate supply voltages and protection features. The need for accuracy has driven the requirement for programmable circuit elements in the control ICs at the heart of the DC to DC converters providing power to these processors. This programmability has been required since the introduction of the first sub 3V supply processors. The advent of digital communication in power subsystems and the emergence of digital control loops in those systems has added significantly to the number of programmable bits required to implement a high performance DC to DC converter. Several technologies can be used to implement this programmability, but the reprogramability and density of NVM technologies make them especially well suited to being the programming element choice in high performance converters.

NVM use in Silicon Clocks
John McDonald, Vice President of Sales and Marketing, SiTime
PDF-VIEW PRESENTATION

Abstract:
Logic NVM can be used in various functions within silicon oscillator products. This presentation will review the decision making process and criteria that SiTime went through in evaluating and selecting the appropriate Logic NVM technology to use in MEMS-based silicon oscillators.

View the complete agenda.

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